module data_ram (
	input [9:0] addr,
	input [31:0] data_w,
	input mem_r_w,
	input clk,

	output [31:0] data_r
);
	reg [31:0] memory[1023:0];

	assign data_r = memory[addr];

	always @ (posedge clk) begin
        if (mem_r_w) begin
            memory[addr] <= data_w;
        end
    end
endmodule